1. Field of the Invention
The present invention relates to a microcomputer, especially to an access method for a CPU to access memories.
2. Description of the Prior Art
FIG. 6 is a block diagram showing the configuration of a conventional microcomputer related to this application. In FIG. 6, numeral 1 is a CPU (central processing unit), 2 is an instruction queue buffer for pre-fetching a command and temporarily store it, and 3 is an internal memory comprising a ROM or RAM.
The above CPU1, instruction queue buffer 2, and internal memory 3 are interconnected by an internal bus 4, composing a one-chip microcomputer 5. Meanwhile, numeral 6 is an external memory installed outside the microcomputer 5, which is connected to the internal bus 4 of the microcomputer 5 by an external bus 7. In general, the internal memory 3 is built in the microcomputer 5 and frequently accessed. Because the capacity of the memory 3 is limited, an expensive high-speed memory is used. The external memory 6 is connected with the microcomputer 5 by the external bus 7. Because the memory 6 requires a large capacity, an inexpensive low-speed memory is used.
Then, operations are described below.
The CPU1 executes an instruction by fetching the instruction code from the instruction queue buffer 2. In this case, unless the requested instruction code is present in the instruction queue buffer 2, the CPU1 skips the instruction queue buffer 2 to fetch the instruction code directly from the internal memory 3 or external memory 6 as shown by a dotted line independently of access to the internal memory 3 or external memory 6 in order to execute the instruction. Thus, memory access can be accelerated. FIG. 7 is a block diagram showing the configuration related to this application of other microcomputer according to the prior art. In FIG. 7, numeral 1 is a CPU, 2 is an instruction queue buffer, and 3a and 3b are internal memories. Number 3a is a high-speed memory comprising a DRAM or SRAM and 3b is a low-speed memory comprising an EPROM. The CPU1, instruction queue buffer 2, and memories 3a and 3b are interconnected by an internal bus 4, composing a one-chip microcomputer 5. Though the EPROM composing the above low-speed memory 3b is low-speed in view of its structure, it is frequently used for microcomputers as a reloadable nonvolatile memory.
The following is the description of the operation of the conventional embodiment.
The CPU1 executes an instruction by fetching the instruction code from the instruction queue buffer 2. In this case, unless the requested instruction code is present in the instruction queue buffer 2, the CPU1 skips the instruction queue buffer 2 to fetch the instruction code directly from the high-speed memory 3a or low-speed memory 3b as shown by a dotted line independently of access to the high-speed memory 3a or low-speed memory 3b in order to execute the instruction. Thus, memory access can be accelerated.
For the memory access method when the requested instruction code is not present in an instruction queue buffer in an conventional microcomputer, an CPU skips the instruction queue buffer to fetch an instruction code directly from the internal or external memory, or high-speed or low-speed memory independently of the high-speed memory such as an internal memory or low-speed memory such as an external memory in FIG. 6, or independently of the high-speed memory and low-speed memory of the internal memories of FIG. 7. Therefore, to fetch the instruction code from the low-speed memory such as an external memory or the internal low-speed memory such as EPROM, the instruction code may not be fetched an error may occur because of severe timing. The speed of a memory depends on the access performance peculiar to the memory element used. However, it is finally determined relatively to the speed of the CPU. Therefore, the above problem easily occurs nowadays because the CPU operation speed is greatly increased according to accelerated operation clock or the like.